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preliminary d atasheet lp 6253 lp 6253 C 0 0 ve rsion 1.0 sep . - 2013 email: marketing@lowpowersemi.com www.lowpowersemi.com page 1 of 11 high efficiency 7 a synchronous boost convertor general description the lp 6253 is a synchronous current mode boost dc - dc converter. its pwm circuitry with built - in 7 a (esop8) c urrent power mosfet mak es this converter highly efficient. selectable high switching frequency allows faster loop response and easy filtering with a low noise output. the non - inverting input its error amplifier is connected to an internal 0. 5 v (tqfn - 16) /0.8 v(esop8) precision refe rence voltage. current mode control and in ternal compensation network make it easy and flexible to stabilize the system. ordering information lp 6253 f: pb - free package type sp: e sop8 qv : t q fn - 1 6 typical application circuit features ? up to 9 6 % efficiency ? output to input disconnect at shutdown mode ? shut - down current:<1ua ? output voltage up to 5 .0 v/3 a (esop8) ? internal compe nsation ? 1. 4 m hz (tqfn - 16) & 800khz(esop8) fixed frequency switching ? high switch on current: 7 a for lp 6253 spf 6 a for lp 6253 qvf ? available in e sop8 and tqfn - 16 package applications ? battery products ? host products ? panel pin configurations marking information device marking package shipping lp 6253 spf LP6253qvf lps lp 6253 ywx esop8 tqfn - 16 3k/reel y: year code. w: week code. x: batch numbers. LP6253qvf l x p g 1 2 3 4 5 6 7 8 e n i l i m g n d f b v o u t v i n p g n d 9 e s o p 8 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 f b v o u t v o u t v o u t l x l x l x l x g n d g n d g n d v i n e n l b o m o d e l b i g n d t q f n - 1 6
preliminary d atasheet lp 6253 lp 6253 C 0 0 ve rsion 1.0 sep . - 2013 email: marketing@lowpowersemi.com www.lowpowersemi.com page 2 of 11 functional pin description esop8 tqfn - 16 pin name description 7 1 fb feed back pin . 6 2 ,3,4 vout output pin. 3 5 ,6,7,8 lx switching p in. 8,9 9,10,11 gnd ground p in. 5 12 vin voltage i nput p in. 13 lbi battery detector input pin. 14 mode enable power save mode. low voltage active. 2 15 en chip enable p in. 16 lbo open_drain low battery detector output pin. 4 pg indication of power good . it is high resistance when vin=0 v , and connecting to ground when vin >3v . 1 ilim by c onnect ion a resistor to ground , set the input current limit . function block diagram ( for LP6253qvf )
preliminary d atasheet lp 6253 lp 6253 C 0 0 ve rsion 1.0 sep . - 2013 email: marketing@lowpowersemi.com www.lowpowersemi.com page 3 of 11 absolute maximum ratings supply input voltage ------------------------------------------------------------------------- --------- ---- ------------------------- 7 v power dissipation, p d @ t a = 25 c e sop8 -- ------------------------------------------- ------------------ -------------------- - --- --- ---------------- ---------------- -- 1.5 w tqfn - 16 - --------------------------------------------- ------------------ -------------------- ---- --------------- -------------- -- -- - 1.5 w package thermal resistance e sop8 , ja ----------------------------------------------------------------------- -- ---------------------------- --- -- ----- -- - 4 6 c/w tqfn - 16 , ja ----------------------------------------------------------------- -- ------ -- ------------------------- --- ----- --- - 45 c/w lead temperature (soldering, 10 sec.) -- ---------------------------- - -- -------------------- -- -- -- --- - ----- - - ------ ------ 260c recommended operating conditions supply input voltage ------------------------------------------------------------ -- --- ---- -- ------- - ----- ---- -- ---- ----- 2. 6 v to 5.5 v en input voltage ----------------------------------------------- ------------------------------- --- -- -------- -- - 0.3 v to vin+0.3 v operation junction temperature range ------------ -------------- ---------------------- - ---------- -- ---- --- ? 40c to 125c operation ambient temperature range -- ------------------- --------------- -- ----------- - --- ------ --- - ---- - --- ? 40c to 85c
preliminary d atasheet lp 6253 lp 6253 C 0 0 ve rsion 1.0 sep . - 2013 email: marketing@lowpowersemi.com www.lowpowersemi.com page 4 of 11 electrical characteristics (vin= 3 . 5 v,vout=5v,cin= 22 uf,cout= 22uf,l =2.2uh ) p arameter conditions lp 6253 units min typ max supply voltage 2. 6 5.5 v output voltage range 2. 6 5.5 v under voltage lockout LP6253qvf, vin voltage decreasing. 1.5 v LP6253spf, vin voltage decreasing. 2.3 supply current(shutdown) ven= 0v 0.05 1 ua supply current LP6253qvf, vfb= 0.6 v 1 9 0 u a feedback voltage LP6253qvf 0.49 0.5 0.51 v LP6253spf 0.784 0.8 0.816 feedback input current vfb= 0.6 v for LP6253qvf 50 na switching frequency LP6253qvf 1200 1 4 0 0 1600 khz LP6253spf 600 800 1000 en input low voltage 0.4 v en input high voltage 1.4 v power mosfet current limit LP6253spf 7 a LP6253qvf 6 a high - side on resistance vout= 5 v 55 m c c
preliminary d atasheet lp 6253 lp 6253 C 0 0 ve rsion 1.0 sep . - 2013 email: marketing@lowpowersemi.com www.lowpowersemi.com page 5 of 11 typical operating characteristics ( for LP6253qvf ) (vin=3.3v vout=5v l=2.2uh cin=22uf cout=22uf) ch1=vout , ch2=vin , ch3=sw ch1=vout , ch2=vin , ch3=sw i load =500ma i load =1000ma ch1=vout , ch2=vin , ch3=sw ch1=vout , ch2=vin , ch3=sw i load =2000ma i load =2500ma ch1=vout, ch2=en, i load = 10ma vin=3.3v, vout=5v, i load =10ma 200ma
preliminary d atasheet lp 6253 lp 6253 C 0 0 ve rsion 1.0 sep . - 2013 email: marketing@lowpowersemi.com www.lowpowersemi.com page 6 of 11 typical operating characteristics ( for LP6253 sp f )
preliminary d atasheet lp 6253 lp 6253 C 0 0 ve rsion 1.0 sep . - 2013 email: marketing@lowpowersemi.com www.lowpowersemi.com page 7 of 11 ope ration information the LP6253 uses a synchronous 1.4mhz /800khz fixed frequency, current - mode regulation architecture to regulate the output voltage. the LP6253 measures the output voltage through an external resistive voltage divider and compares that to the internal 0.5v /0.8v reference to generate the error voltage to the inductor current to regulate the output voltage. the use of current - mode regulation improves transient response and control loop stability. the peak current of the nmos switch is also se nsed to limit the maximum current flowing through the switch and the inductor. the typical peak current limit is set to 7 a (LP6253spf) . an internal temperature sensor prevents the device from getting overheated in case of excessive power dissipation . the de vice integrates an n - channel and a p - channel mosfet transistor to realize a synchronous rectifier. because the commonly used discrete schottky rectifier is replaced with a low r ds(on) pmos switch, the power conversion efficiency reaches 9 6 %. to avoid groun d shift due to the high currents in the nmos switch, two separate ground pins are used. the reference for all control functions is the gnd pin. the source of the nmos switch is connected to pgnd. both grounds must be connected on the pcb at only one point close to the gnd pin. a special circuit is applied to disconnect the load from the input during shutdown of the converter. in conventional synchronous rectifier circuits, the backgate diode of the high - side pmos is forward biased in shutdown and allows cu rrent flowing from the battery to the output. this device however uses a special circuit which takes the cathode of the backgate diode of the high - side pmos and disconnects it from the source when the regulator is not enabled (en = low). the b enefit of thi s feature for the system design engineer is that the battery is not depleted during shutdown of the converter. no additional components have to be added to the design to make sure that the battery is disconnected from the output of the converter. device e nable the device is put into operation when en is set high. it is put into a shutdown mode when en is set to gnd. in shutdown mode, the regulator stops switching, all internal control circuitry including the low - battery comparator is switched off, and the load is isolated from the input ( as described in the synchronous rectifier section). this also means that the output voltage can drop below the input voltage during shutdown. during start - up of the converter, the duty cycle and the peak current are limited in order to avoid high peak currents drawn from the battery. undervoltage lockout an under voltage lockout function prevents device start - up if the supply voltage on vbat is lower than approximately 1.5 v (LP6253qvf) & 2.3v(LP6253spf) . when in operation an d the battery is being discharged, the device automatically enters the shutdown mode if the voltage on vbat drops below approximately 1.5 v. this undervoltage lockout function is implemented in order to prevent the malfunctioning of the converter. softsta rt (for LP6253qvf) when the device enables the internal start - up cycle starts with the first step, the precharge phase. during precharge, the rectifying switch is turned on until the output capacitor is charged to a value close to the input voltage. the re ctifying switch current is limited in that phase. this also limits the output current under short - circuit conditions at the output. after charging the output capacitor to the input voltage the device starts switching. until the output voltage is reached, t he boost switch current limit is set to 40% of its nominal value to avoid high peak currents at the battery during startup. when the output voltage is reached, the regulator takes control and the switch current limit is set back to 100%. power save mode (f or LP6253qvf) the mode pin can be used to select different operation modes. to enable power save, mode must be set low. power save mode is used to improve efficiency at light load. in power save mode the converter only operates when the output voltage tri ps below a set threshold voltage. it ramps up the output voltage with one or several pulses and goes again into power save mode once the output voltage exceeds the set threshold voltage. this power save mode can be disabled by setting the mode to vbat.
preliminary d atasheet lp 6253 lp 6253 C 0 0 ve rsion 1.0 sep . - 2013 email: marketing@lowpowersemi.com www.lowpowersemi.com page 8 of 11 low battery detection ---- lbi/lbo (for LP6253qvf) the LP6253 low - battery detector circuit is typically used to supervise the battery voltage and to generate an error flag when the battery voltage drops below a user - set threshold voltage. the function is active only when the device is enabled. when the device is disabled, the lbo pin is high - impedance. the switching threshold is 500 mv at lbi. during normal operation, lbo stays at high impedance when the voltage, applied at lbi, is above the threshold. it is active low when the voltage at lbi goes below 500 mv . the battery voltage, at which the detection circuit switches, can be programmed with a resistive divider connected to the lbi pin. the resistive divider scales down the battery voltage to a voltage l evel of 500 mv, which is then compared to the lbi threshold voltage. the lbi pin has a built - in hysteresis of 10 mv , if the low - battery detection circuit is not used, the lbi pin should be connected to gnd (or to vbat) and the lbo pin can be left unconnecte d. do not let the lbi pin float. the recommended value for r2 is therefore in the range of 500 k?. from that, the value of resistor r1, depending on the desired minimum battery voltage vbat , can be calculated using : LP6253 qv f:r1=(vbat/0. 5 v - 1) r2 setting the output voltage set the output voltage by selecting the resistive voltage divider rati o. the voltage divider drops the output voltage to the 0.5v (LP6253qvf)/ 0.8v(LP6253spf) feedback voltage. use a 10k resistor for r4 of the voltage divider. determine the high - side resistor r3 by the equation: vout=(r3/r4+1) v fb low - emi switch th e device integrates a circuit that removes the ringing that typically appears on the sw node when the converter enters discontinuous current mode. in this case, the current through the inductor ramps to zero and the rectifying pmos s witch is turned off to prevent a reverse current flowing from the output capacitors back to the battery. due to the remaining energy that is stored in parasitic components of the semiconductor and the inductor, a ringing on the sw pin is induce d. the integrated antiringing sw itch clamps this voltage to vbat and therefore dampens ringing. pre - boost current and short circuit protect initially output voltage is lower than battery voltage, and the LP6253 enters pre - boost phase. during pre - boost phase, the internal nmosfet/pmosfe t is turned off/on and a constant current is provided from battery to output until the output voltage close to the battery voltage. the constant current is limited by internal controller. if the output short to ground, the LP6253 also limits the output cur rent to avoid damage condition. inductor selection for a better efficiency in high switching frequency converter, the inductor selection has to use a proper core material such as ferrite core to reduce the core loss and choose low esr wire to reduce copp er loss. the most important point is to prevent the core saturated when handling the maximum peak current. using a shielded inductor can minimize radiated noise in sensitive applications. the maximum peak inductor current is the maximum input current plus the half of inductor ripple current. the calculated peak current has to be smaller than the current limitation in the electrical characteristics. a typical setting of the inductor ripple current is 20% to 40% of the maximum input current. if the selection is 40%, the maximum peak inductor current is the minimum inductance value is derived from the following equation : depending on the application, the recommended inductor value is between 2.2h to 10h. input capacitor selection for better input byp assing, low - esr ceramic capacitors are recommended for performance. a 10f input capacitor is sufficient for most applications. a ceramic capacitor or a tantalum capacitor with a 100nf ceramic capacitor in parallel,
preliminary d atasheet lp 6253 lp 6253 C 0 0 ve rsion 1.0 sep . - 2013 email: marketing@lowpowersemi.com www.lowpowersemi.com page 9 of 11 placed close to the ic, is recommended . for a lower output power requirement application, this value can be decreased. output capacitor selection for lower output voltage ripple, low - esr ceramic capacitors are recommended. the tantalum capacitors can be used as well, but the esr is bigger th an ceramic capacitor. the output voltage ripple consists of two components: one is the pulsating output ripple current flows through the esr, and the other is the capacitive ripple caused by charging and discharging. the major paramet er necessary to define the output capacitor is the maximum allowed output voltage ripple of the converter. this ripple is determined by two parameters of the capacitor, the capacitance and the esr. it is possible to calculate the minimum capacitance needed for the defined ripple, supposing that the esr is zero, by using equation: layout guideline for high frequency switching power supplies, the pcb layout is important step in system application design. in order to let ic achieve good regulation, high eff iciency and stability, it is strongly recommended the power components should be placed as close as possible. the set races should be wide and short. the feedback pin and then works of feedback and compensation should keep away from the power loops, and be shielded with a ground trace or plane to prevent noise coupling. implementation of integrated circuits in low - profile and fine - pitch surface - mount packages typically requires special attention to power dissipation. many system - dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat - generating components affect the power - dissipation limits of a given component. three basic approaches for enhancing thermal performance are listed below: improving the power dissipation capability of the pcb design ; improving the thermal coupling of the component to the pcb ; introducing airflow in the system .
preliminary d atasheet lp 6253 lp 6253 C 0 0 ve rsion 1.0 sep . - 2013 email: marketing@lowpowersemi.com www.lowpowersemi.com page 10 of 11 packaging information
preliminary d atasheet lp 6253 lp 6253 C 0 0 ve rsion 1.0 sep . - 2013 email: marketing@lowpowersemi.com www.lowpowersemi.com page 11 of 11 esop8

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